1. Field of the Invention
The present invention relates to a drive circuit for a display panel and an image display device using the drive circuit.
2. Description of the Prior Art
An image display device such as a liquid crystal display device includes a display panel where pixel circuits corresponding to respective pixels are arranged two-dimensionally. The display panel includes gate lines corresponding to respective scanning lines for the pixels. The gate lines are connected to a gate line drive circuit on a side of a display area. The gate line drive circuit includes a shift register which outputs a voltage enabling writing data into the pixel circuits sequentially for each scanning line.
The shift register used in the gate line drive circuit or the like can be formed on a side of the display area of the display panel. In this case, the shift register is formed using thin film transistors (TFT) where a semiconductor layer is formed using amorphous silicon (a-Si) on the same substrate as the pixel circuits.
The shift register is constituted of unit register circuits (unit drive circuits) in plural stages which are connected by a cascade junction. Basically, the unit register circuit on each stage performs an operation of outputting a selective pulse one time sequentially from one end to the other end of a unit register circuit column in vertical scanning or the like. That is, each of the plurality of basic register circuits which constitute the shift register provided to the gate line drive circuit, during 1 frame period, outputs a High (H) level which is a predetermined positive potential as a selective pulse only when the pixel circuits which are arranged along the scanning line corresponding to the basic register circuit are controlled, and outputs a Low (L) level which is a predetermined negative potential as a selective pulse during the most period corresponding to other scanning lines.
FIG. 6 is a circuit diagram of a basic register circuit according to a prior art. Each transistor which constitutes the circuit is turned on when a potential of an H level is applied to a gate thereof, and is turned off when a potential of an L level is applied to the gate thereof. In an initial state, a node N1 is set to an L level, and a node N2 is set to an H level. An output transistor T5 is connected between an output terminal OUT of a unit register circuit in a k-th stage and a clock signal line CLK(k), and a transistor T6 is connected between the terminal OUT and a power source VGL at an L level.
The unit register circuits which constitute the shift register generate an output pulse sequentially. When an output pulse G(k−1) of a preceding stage is inputted to the unit register circuit in a k-th stage, the node N1 (one end of a capacitor C1) is connected to a power source VGH so that a potential at the node N1 becomes an H level whereby the transistor T5 is turned on. In a state where a potential at the node N1 is at the H level, the node N2 is connected to the power source VGL so that a potential at the node N2 becomes an L level whereby the transistor T6 is turned off. During a period where the transistors T5 and T6 are in such a state (outputting operation period), the potential at the output terminal OUT is determined corresponding to a clock signal CLK(k). That is, when a pulse of an H level is outputted to the clock signal CLK(k), during the pulse outputting period, the potential at the node N1 is further elevated through the capacitor C1 connected between a source and a gate of the transistor T5 so that a pulse Gk of an H level is generated at the output terminal OUT.
The unit register circuit in a (k+1)th stage, when the output pulse Gk of k-th stage is inputted to the unit register circuit in the (k+1)th stage, is operated in the same manner as the unit register circuit in the k-th stage, and generates an output pulse G(k+1) in synchronism with a pulse of a clock signal CLK(k+1). Further, the unit register circuit in a (k+2)th stage generates an output pulse G (k+2) in synchronism with a pulse of a clock signal CLK(k+2).
When the output pulse G(k+2) of the (k+2)th stage is inputted to the unit register circuit in a k-th stage, the node N1 is connected to the power source VGL so that the potential at the node N1 becomes an L level again. At the same time, the node N2 is connected to the power source VGH in response to the pulse of the clock signal CLK(k+2) and a potential at the node N2 becomes an H level again.
In this manner, during the period other than the outputting operation period, the node N1 is an L level, the node N2 is an H level, the transistor T5 is in an OFF state, and the transistor T6 is in an ON state. In such a state, a potential at the output terminal OUT is set to an L level given by the power source VGL.
A pulse of a clock signal CLK is supplied to a drain of the transistor 15 even during period other than the outputting operation period, and the pulse tries to elevate the potential at the node N1 through a capacitor between the gate and the drain of the transistor T5. A transistor T2 connected between the node N1 and the power source VGL is in an ON state when a potential of an H level at the node N2 is applied to the gate terminal during a period other than the output operation period so that the elevation of the potential at the node N1 described above is prevented.